Power management in a data processing device having masters and slaves

ABSTRACT

A device, such as an integrated circuit is described including master units, and slave units connected by an interconnect. In addition to the normal data signals and address signals passed with a transaction, there are also passed usage signals which specify the time interval until a next transaction will be sent to a slave unit. A local slave power controller is responsive to such usage signals to switch into a low power mode and pre-emptively switch back to an operational mode in time to respond to the next transaction to be received.

This application is the U.S. national phase of International ApplicationNo. PCT/GB2006/002830 filed 28 Jul. 2006 which designated the U.S., theentire contents of which are hereby incorporated by reference.

This technology relates to the field of data processing devices, andmore particularly, to the management of power consumption within suchdevices.

Power consumption in system-on-chip integrated circuits and devices suchas portable telephones and computers, is a major concern. Even innon-portable devices, reducing power dissipation is important because itreduces cost, simplifies the design of cooling, packaging and powersupplies and increases reliability.

Known power management schemes fall into two main groups. The first andmost common kind are heuristic power management policies, such as idletimeouts, for example turning off a display or turning down a CPU clockafter some period of inactivity. The second kind are schemes thatattempt to predict, using stochastic or Markov models, for example, whena device will not be used and suspend it. This type of schemeencompasses adaptive frequency and voltage scaling controlled at anoperating system level.

A survey of known power management schemes can be found in “A Survey ofDesign Techniques For System Level Dynamic Power Management” by LucaBenini et al, IEEE Transactions On Very Large Scale Integration (VLSI)Systems, Volume 8, No. 3, June 2002.

A problem with all of the above schemes is that they tend to induce somepower-delay trade off, i.e. they save power, but increase latency. Themanagement of power in system-on-chip systems that contain manyprocessing units and peripherals is particularly difficult. For example,a shared peripheral, such as a memory, might be used by a particularprocessor at a particular time interval, but might be required at lowlatency by another processor during that interval. Known schemes, suchas the AMBA 3 AXI power management channel and the IEEE 802.11 wirelessprotocol, rely on a single power manager to resolve such system powerissues. These centralized schemes do not scale well to larger systems.Integration of the power management signalling, which is routeddifferently to the main communication buses also represents anadditional overhead and presents difficulties.

Viewed from one aspect the technology described herein provides a devicefor processing data comprising:

one or more master units;

one or more slave units; and

an interconnect coupled to said one or more master units and said one ormore slave units so as to route transactions, including data transfertransactions, along a wired path between said one or more master unitsand said one or more slave units; wherein

a transaction received by at least one of said one or more slave unitsincludes one or more usage signals specifying a usage predictionindicative of when a next transaction will be sent to said at least oneof said one or more slave units; and

said at least one of said one or more slave units has a local slavepower controller responsive to said one or more usage signals to switchsaid at least one of said one or more slave units to a first slave powerstate for an interval before said next transaction is expected to bereceived and to switch said at least one of said one or more slave unitsto a second slave power state in time to service said next transaction,said first slave power state having a lower power consumption than saidsecond slave power state and said first slave power state having aresponse latency longer than said second slave power state.

The present technique attempts to manage power with a reducedpower-delay trade off by enabling a substantially precise indication ofthe period for which a device will be inactive to be signalled at amicro-architectural level. This removes the requirement for complex andimprecise heuristic and/or predictive models. The present techniquedelegates power management to the individual slaves and masters. It isreadily scalable since it does not require an associated complex centralpower controller.

In preferred embodiments the power management signals can be routedtogether with the other communication signals to ease implementation andscalability, although more generally the usage signals could have theirown separated routing/bus. The wired path could be a combined bus withvarious signals routed together or several separate buses with their ownrouting. Incorporating the power management signalling as part of thestandard communication aids scalability.

The usage signals can be generated or modified (arbitrated) at differentpoints between a transaction being initiated and the target for thattransaction. One important source of usage signals is a master unitissuing a transaction since the master unit would likely be able toaccurately identify when it was next to issue a transaction to thatslave and accordingly incorporate appropriate usage signals along withthe transaction. Another appropriate point for inserting or modifyingusage signals would be at the level of the interconnect, which wouldlikely have information relating to the state of the device as a whole,e.g. due to arbitration decisions made within the interconnect it may bepossible to determine that usage of a given slave would be unlikely tobe repeated for a period longer than would be indicated by the masterinitiating that transaction.

The interconnect can in preferred embodiments provide the function ofarbitrating between usage signals received with respective transactionsfrom a plurality of master units to provide an arbitrated usage signalpassed to the target slave device. The interconnect is in a position totake account of previous transactions to a slave and previous usageinformation as well as the information associated with a currenttransaction in determining what usage signals to pass to a target slavedevice.

The level of sophistication provided at a slave unit can vary andadvantageously a slave unit will have a plurality of low power stateswith respective power consumptions and response latencies, typically thelower the power consumption then the higher the latency. Depending uponthe interval before the next transaction is predicted to arrive, theslave unit can choose the appropriate power down mode to enter, e.g. itmay not be worthwhile entering a very deep power down mode which takes along time to enter and a long time to exit when the interval to the nexttransaction is short, but it might be worthwhile to simply stop theclock for that short period to save some power.

The local slave power controller, which can advantageously be shared bya plurality of slave units can also select the low power state independence upon the slave unit's current state as well as the intervalto the next transaction, e.g. there may be some other state variableassociated with the slave unit concerned, such as servicing some otheractivity unconnected with the particular transaction, which indicatesthat the slave unit is unable to power down to a particular low powermode which is indicated by the interval to the next transaction.

It will be appreciated that whilst the above is described and useful interms of only one slave unit incorporating an appropriate focal slavepower controller, the technique is readily scalable and advantageous insystems in which multiple slave units contain respective local slavepower controllers responsive to the usage signals. Similarly, thetechnique is well suited to systems incorporating multiple appropriatelyconfigured master units for generating usage signals.

In accordance with a preferred technique at least one of said one ormore slave units upon receipt of a transaction from one of said one ormore master units issues an acknowledgement to said one of said one ormore master units, said acknowledgement including one or more delaypredicting signals indicative of when said at least one of said one ormore slave units will complete said transaction to said one of said oneor more master units, and

said one of said one or more master units includes a local master powercontroller responsive to said one or more delayed predicting signals toswitch said one of said one or more master units to a first master powerstate for an interval before completion of said transaction is expectedand to switch said one of said one or more master units to a secondmaster power state in time for completion of said transaction, saidfirst master power state having a lower power consumption than saidsecond master power state and said first master power state having aresponse latency longer than said second master power state.

The intelligent and deterministic powering down of slave units inaccordance with usage signals can be extended backwards to the masterunits. An acknowledgement signal returned from a slave unit (possiblyreusing the usage signal lines/connection) upon receipt of a transactioncan indicate how long it will be before the slave unit is able tocomplete that transaction and accordingly there is the possibility forthe master unit to enter a lower power mode pending completion of thetransaction e.g. latency in servicing a memory fetch.

As well as being used to control the power mode of a master and a slaveinvolved in a given transaction, the present technique and the usagesignals can also serve to trigger one or more intervening circuits on apath between the slave and master to enter a reduced power consumptionstate. This may include portions of an interconnect where it is knownthat that portion will be dormant for a determined period as indicatedby the usage signals. This can save further power.

The usage signals can represent the delays in a variety of differentways, but a useful trade off between the number of usage signals whichneed to be provided and the range of delays which can be represented isone where a logarithmic encoding is employed. The lowest non-zero valuerepresentable can be selected to correspond to the lowest effectiveinactivity interval of any of the slaves which may be communicated withas it would not be worthwhile communicating potential power downintervals smaller than the lowest such interval which was usable.

When the time until a next transaction is indeterminate, this can alsobe communicated by the usage signals and a local slave power controllercan be responsive thereto to switch to a low power consumption mode ifdesired. It will be appreciated that some latency will be associatedwith such indeterminate time intervals since it will not be possible forthe slave unit to preemptively power up in time for the nexttransaction.

The manner in which the sources of usage signals can select which usagesignals to assert can vary. In one type of embodiment a usage-specifyingregister may be associated with the master unit and writable undersoftware control with a value specifying which usage signals should begenerated in association with transactions originating at that masterunit. This gives a good deal of flexibility in the way in which theusage signals may be specified, but at the cost of requiring somesoftware intervention. Such software programming of the usage values maybe performed at power up or system initialisation.

As an alternative, or in addition to, the above use of a register tospecify usage signals, usage signal values may also be encoded withinprogram instructions executed on a processor serving as a master andinitiating a transaction. Accordingly, each transaction can have its ownusage signal associated with it which was determined at the time thesoftware was written, such as automatically by the compiler, with aknowledge of when the next transaction to be initiated by that programwould arise.

A still further alternative, or addition, would be where an operatingsystem program monitoring parameters of the system, such as threadactivity, would determine what usage values to specify and use anappropriate program instruction to associate such usage values with atransaction being issued to a slave.

In addition to transferring information regarding the interval to thenext transaction, the usage signals can also be used to pass powercommands, such as local shutdown, global shutdown, local sleep, globalsleep, local clock stop, global clock stop, local clock speedspecifying, global clock speed specifying, low operating voltage mode,low leakage mode, wakeup and/or interval extend. The usage signals arealready routed through the interconnect and accordingly provide aconvenient vehicle for passing such power commands around the system.

It will be appreciated that the present technique can be applied todevices having a wide variety of different forms. The technique isparticularly well suited to use within integrated circuits or multi-chipmodules, but is extendible to printed circuit boards carrying aplurality of connected integrated circuits, e.g. a particularly powerhungry slave would be an off-chip memory and it might be desirable topower this down using the usage signal technique described above.

Whilst the interconnect could take many forms, including a dedicatedconnection between one master unit and one slave unit, such as between aprocessor core and a cache memory, the technique is extendible andparticularly applicable in the environment of interconnects providing amore generic point-to-point connection, such as for example the AXIinterconnect systems provided by ARM Limited of Cambridge, England.

Viewed from another aspect the technology described herein provides amethod for processing data using one or more master units, one or moreslave units and an interconnect coupled to said one or more master unitsand said one or more slave units so as to route transactions, includingdata transfer transactions, along a wired path between said one or moremaster units and said one or more slave units, said method comprisingthe steps of:

generating a transaction received by at least one of said one or moreslave units, said transaction includes one or more usage signalsspecifying a usage prediction indicative of when a next transaction willbe sent to said at least one of said one or more slave units; and

in response to said one or more usage signals using a local slave powercontroller of said at least one of said one or more slave units toswitch said at least one of said one or more slave units to a firstslave power state for an interval before said next transaction isexpected to be received and to switch said at least one of said one ormore slave units to a second slave power state in time to service saidnext transaction, said first slave power state having a lower powerconsumption than said second slave power state and said first slavepower state having a response latency longer than said second slavepower state.

Viewed from a further aspect the technology described herein provides adevice for processing data comprising:

one or more master unit means;

one or more slave unit means; and

an interconnect means coupled to said one or more master units and saidone or more slave units so as to route transactions, including datatransfer transactions, along a wired path between said one or moremaster unit means and said one or more slave unit means; wherein

a transaction received by at least one of said one or more slave unitmeans includes one or more usage signals specifying a usage predictionindicative of when a next transaction will be sent to said at least oneof said one or more slave unit means; and

said at least one of said one or more slave nit means has a local slavepower controller means responsive to said one or more usage signals toswitch said at least one of said one or more slave unit means to a firstslave power state for an interval before said next transaction isexpected to be received and to switch said at least one of said one ormore slave unit means to a second slave power state in time to servicesaid next transaction, said first slave power state having a lower powerconsumption than said second slave power state and said first slavepower state having a response latency longer than said second slavepower state.

Viewed from a further aspect the technology described herein provides aslave unit for use within a device having one or more master units, oneor more slave units and an interconnect coupled to said one or moremaster units and said one or more slave units so as to routetransactions, including data transfer transactions, along a wired pathbetween said one or more master units and said one or more slave units,a transaction to received by at least one of said one or more slaveunits including one or more usage signals specifying a usage predictionindicative of when a next transaction will be sent to said at least oneof said one or more slave units, said slave unit comprising:

a local slave power controller responsive to said one or more usagesignals to switch said at least one of said one or more slave units to afirst slave power state for an interval before said next transaction isexpected to be received and to switch said at least one of said one ormore slave units to a second slave power state in time to service saidnext transaction, said first slave power state having a lower powerconsumption than said second slave power state and said first slavepower state having a response latency longer than said second slavepower state.

Viewed from a further aspect the technology described herein provides amaster unit for use within a device having one or more master units, oneor more slave units and an interconnect coupled to said one or moremaster units and said one or more slave units so as to routetransactions, including data transfer transactions, along a wired pathbetween said one or more master units and said one or more slave units,said master unit comprising:

a transaction generator configured to generate a transaction to bereceived by at least one of said one or more slave units and includingone or more usage signals specifying a usage prediction indicative ofwhen a next transaction will be sent to said at least one of said one ormore slave units.

Viewed from a further aspect the technology described herein provides aninterconnect for use within a device having one or more master units,one or more slave units and an interconnect coupled to said one or moremaster units and said one or more slave units so as to routetransactions, including data transfer transactions, along a wired pathbetween said one or more master units and said one or more slave units,said interconnect comprising:

a signal connection configured to pass a transaction to be received byat least one of said one or more slave units and including one or moreusage signals specifying a usage prediction indicative of when a nexttransaction will be sent to said at least one of said one or more slaveunits.

FIG. 1 schematically illustrates a device utilising power managementtechniques;

FIG. 2 schematically illustrates parallel signals passed via aninterconnect in association with a transaction between a master and aslave;

FIG. 3 schematically illustrates one example encoding of usage signals;

FIG. 4 schematically illustrates a slave unit incorporating a localslave power controller;

FIG. 5 schematically illustrates a local slave power controller;

FIG. 6 is a flow diagram schematically illustrating the operation of alocal slave power controller;

FIG. 7 schematically illustrates a master unit incorporating a localmaster power controller;

FIG. 8 is a flow diagram schematically illustrating the operation of alocal master power controller;

FIG. 9 is a diagram schematically illustrating an interconnectincorporating a usage signal arbitration function; and

FIG. 10 is a flow diagram schematically illustrating usage signalarbitration.

FIG. 1 shows a device 2 in the form of a printed circuit boardincorporating an integrated circuit 4 and a slave subsystem 6. Theintegrated circuit 4 may be a multi-chip module, a system-on-chipintegrated circuit or a standard integrated circuit. The integratedcircuit incorporates a master unit 8, a processor core 10, which alsoserves as a master, and a cache memory 12 coupled to the processor core10. The cache memory 12 serves as a slave to the processor core 10 andalso as a master to an interconnect 14. Between the processor core 10and the cache memory 12 there is a dedicated interconnect 16 whichpasses usage signals in accordance with the present technique asdescribed below. The interconnect 14 is in this example embodiment amodified form of a AXI interconnect incorporating point-to-pointconnectivity and arbitration functions for such connections inaccordance with the known AXI techniques. The interconnect 14 isextended beyond this known functionality by the provision of usagesignals in accordance with the present technique which pass anindication of when a slave unit, such as one of the slaves 18, 20, 6will receive its next transaction. The slave sub-system 6 acts as aslave relative to the interconnect 14, but in itself has more than oneassociated functional element which may be used, or not used, dependingupon the transaction concerned and require further signal routing. Theslave subsystem 6 could be a memory system with some local memory andadditionally some higher order memory, such as a hard disk drive whichwould be required when the local memory could not service a particulartransaction.

FIG. 2 schematically illustrates signals forming part of a transactionpassed by the interconnect 14. These signals include data signals 22,address signals 24 and usage signals 26. The address signals 24 and thedata signals 22 can be in accordance with the known AXI systems andprotocols and may be routed (separately or together) and arbitratedbetween in accordance with these known system protocols. The usagesignals 26 are added to this transaction and can follow the same routingso as to be subject to the same routing arbitration and delays. Theusage signals 26 may alternatively be provided separately with their ownrouting and arbitration. The usage signals 26 pass informationspecifying, when this is known, when the next transaction originatingfrom that master and passing to the target slave unit will occur. Thisinformation can be used by the slave to power itself down to anappropriate power down mode and preemptively power itself back up intime to service that next transaction without incurring disadvantageouslatency.

FIG. 3 schematically illustrates one example encoding which may be usedfor example 3-bit usage signals. This encoding is logarithmic for allbut the first and last values. The first value specifies no predictedinterval and indicates that the slave should stay active. The lastencoding represents an indeterminate interval and may be interpreted bythe slave in a variety of different ways, such as initiating a sleepmode with no pre-emptive power up. In between these extremes, theencoding represents the interval to the next transaction, expressed interms of a multiple of the minimum supported power down interval, suchas four clock cycles in the case of a typical AXI interconnectimplementation. There is no need to provide a granularity smaller thanthis smallest interval.

FIG. 4 schematically illustrates a slave unit 28. This incorporates anumber of functional blocks 30, 32 which process the transactionreceived in accordance with the functionality provided by that slaveunit 28 and in substantially the normal way as expected for an AXItransaction. In addition, a local slave power controller 34 is providedwhich is responsive to the usage signals and state information passedfrom functional block 30 to determine whether it is appropriate to enterone of a plurality of power down modes subsequent to servicing areceived transaction, and for how long that power down mode should beentered. If the slave unit 28 is to be powered down, then appropriateclock control signals and/or voltage control signals are supplied to thefunction blocks 30, 32 to initiate this power down and subsequentlyinitiate a pre-emptive power up. A local slave power controller 34 mayalso be shared by a plurality of slave units.

FIG. 5 schematically illustrates the local slave power controller 34 inmore detail. The usage signals are supplied to power control logic 36together with state variables representing one or more aspects of thecurrent state of the slave unit 28. These signals in combination areused to determine into which powered down mode the slave unit 28 shouldbe placed and for what time period. In accordance with this, anappropriate timer value is loaded into a timer 38 which then counts downthe passage of time (e.g. in units of the minimum power down interval)until the pre-emptive wakeup is required and then generates a wakeupsignal which is passed to the power control logic 36. The clock controlsignals and the voltage control signals generated by the power controllogic 36 to enter the appropriate power down mode can have a variety ofdifferent effects. The clock signal could be stopped or slowed to adifferent value. The voltage could be lowered or switched off. Thesystem could be placed into a low leakage mode or some other voltagemanipulation performed to reduce power. Various power down modes areknown and of any these could be used.

FIG. 6 is a flow diagram schematically illustrating the controlperformed by the power control logic 36. At step 40 the system waits forusage signals to be received. When such signals are received, processingat step 42 selects the power down mode to be entered depending upon thelength of the interval until the next transaction and the current slavestate. If the interval is short, then it may not be worthwhile enteringa deep power down mode, which takes a large amount of time to enter andexit. Similarly, the current state of the slave unit 28 may placelimitations on the power down modes which may be entered (signalled byits state variables) independently of the interval indicated. When thepower down mode has been selected, then the wakeup time can bedetermined. Different power down modes will require different longeramounts of time to exit and accordingly require the wakeup to occurearlier or later. At step 44, the timer 38 is loaded with the intervalto the required wakeup point. Step 46 then checks whether the currenttransaction, which accompanied the usage signals which were detected atstep 40, has completed. When this transaction has completed, processingproceeds to step 48 at which the signals for controlling the clock andvoltage appropriate to the selected power down mode are issued and theslave unit is switched into that power down mode. Step 50 continuouslychecks whether the timer has reached the required wakeup point. When thewakeup point is reached, then processing proceeds to step 52 at whichthe wakeup is initiated and the power control logic 36 issues theappropriate clock control and voltage control signals to move the slaveunit 28 back to its operational mode in which it is able to respond tothe next transaction. The aim of the power control logic 36 will be tomove the slave unit 28 back to its operational mode so that it is readyfor the next transaction just in time for that next transaction to bereceived.

Although not illustrated in FIG. 6, the slave unit 28 may utilise theusage signals to send back an acknowledgement to the initiating masterindicating how long it will be before the slave unit 28 is able tocomplete the just received transaction. This acknowledgement signal isused by the master to power itself down if appropriate pending receiptof the completed transaction with the master unit powering itself uppreemptively in time to receive the completed transaction.

FIG. 7 schematically illustrates a master unit 54. The master unit 54incorporates one or more functional blocks 56, 58 generatingtransactions, such as AXI transactions, in substantially the known wayand being responsive to program instructions if they are programmable.Also, provided within the master unit 54 is a local master powercontroller 60. The local master power controller 60 is responsive to oneor more of a software writable interval value stored within an intervalregister 62; decoded signals from a field within a program instructiongiving a decoded interval on signal line 64; and state variable signals66 specifying the current state of the master unit 54, in determiningwhat usage signals 68 to issue in association with a transaction sentout from the master unit 54 to a slave-unit. The usage signals willspecify when the master unit 54 expects it will next initiate atransaction to that slave. This indicated usage signal value isdetermined at a micro-architectural level within the master unit 54itself and so will tend to be relatively accurate, although this cannotbe absolutely guaranteed, e.g. due to the occurrence of unexpectedinterrupts.

The local master power controller 60 is also responsive toacknowledgement signals passed back from a slave via the usage signallines 68 to power down the master unit 54 when the slave indicates thatit will not be completing a transaction, e.g. returning requested data,for a period justifying entry and exit from a power down mode. The localmaster power controller accordingly generates clock control signals andvoltage control signals which are passed to the functional blocks 56, 58to enter power down modes within the master 54.

FIG. 8 schematically illustrates the control performed by the localmaster power controller 60. At step 70 the processing waits for atransaction needing to be issued. When a transaction is to be issued,then step 72 determines the interval to be specified in the usagesignals which will accompany that transaction from the shortest of theinterval specified by the interval register value within the register62; the decoded interval from any program instruction on the decodedinterval signal lines 64; and in dependence upon any constraintspecified by the state variables on the state variable signal line 66.When this determination is complete, step 74 issues the usage signals onsignal lines 68 together with a transaction. Step 76 waits for anyacknowledgement signals which might be passed back from the slaveindicating how long it will be before the slave is able to complete thetransaction. If such acknowledgement signals are received, thenprocessing passes to step 78 where a determination of the power downmode to be employed is made as selected from a plurality of power downmodes which might be supported by the particular master unit 54, e.g.clock stopping, clock slowing, low voltage, low leakage, sleep, powerdown, data retention etc. At step 80, the interval to the requiredwakeup time associated with the power down mode to be used is determinedand loaded into a timer within the local master power controller 60. Atstep 82, the local master power controller 60 switches the master unit54 into the power down mode. At step 84, the local master powercontroller 60 waits until the timer reaches a wakeup point at which timeprocessing progresses to step 86 and the master unit 54 is switched backto its operation mode in time for the data to be returned or thetransaction completed in some other way.

FIG. 9 schematically illustrates an interconnect block 14 which may beused in accordance with the present technique. This interconnect block14 supports the routing of address and data as well as controlinformation in accordance with the known AXI techniques, or othertechniques. The elements included within the interconnect 14 to supportthese known functions are not described herein further as they will befamiliar to those in this technical field. The interconnect 14 inaddition to its normal elements includes an interconnect usage signalarbitration block 88 which serves to arbitrate usage signals passingthrough the interconnect 14 between masters and slaves. A timer 90provides a time index value incrementing in minimum power down intervalsteps e.g. four clock cycles. When a usage signal is received inassociation with a transaction, a determination is made as to whether ornot the stored time index values associated with the connected mastersand indicating when those masters will next require the particular slaveconcerned indicate such a next usage before or after that indicated bythe current received usage signal for the target slave unit. Thesestored time index values are held within registers 92 and 94. If thestored next usage requirement is prior to that indicated in thecurrently received usage signals, then the interconnect usage signalarbitration block 88 will modify the usage signal and replace theinterval it specifies with a shorter interval as indicated by one of thestored next usage values within the registers 92, 94. If the next usageindicated by the current received usage signals is prior to any of thosestored, then it will be passed on unaltered together with thetransaction.

It will be appreciated that the arbitration between multiple masters isin this example performed within the interconnect 14. As an alternative,the arbitration could be performed within a slave unit itself,particularly if that slave unit was of a more complicated type, such asa memory controller, which was already designed and had systems providedfor dealing with overlapping transactions from multiple masters.

The interconnect 14 in providing its data and address routing functionsincorporates a variety of different portions, which can be selectivelypowered up and powered down in response to the usage signals passingthrough the interconnect 14. The interconnect block 14 can determinefrom the usage signals it is passing that a particular path will not berequired for a certain period and accordingly it can power down thatpath whether that be parts of itself or additional parts outside of theinterconnect block and not subject to their own local power control inresponse to usage signals passing therethrough.

FIG. 10 is a flow diagram schematically illustrating the arbitrationperformed by the interconnect usage signal arbitration block 88. At step96 the interconnect usage signal arbitration block 88 waits for atransaction. When such a transaction is received, step 98 compares thenext usage time derived from the usage signals concerned in the receivedtransaction with the next usage time indexes for the other masters forpreviously received transactions from those other masters as storedwithin the registers 92, 94. Step 100 then determines whether any othermasters have indicated a shorter interval to the next usage. If anyother masters do have a shorter interval, then processing proceeds tostep 102, which is otherwise by passed, at which the usage signalsreceived are modified to instead represent the shortest interval for anyof the masters of which the interconnect block 14 is aware and inresponse to any additional delay that may be imposed by the interconnectblock 14 itself. The interconnect usage signal arbitration block 88 isresponsive to state variable signals specifying the state of theinterconnect block 14 and which can indicate factors such as that thedata and address routing blocks operating in accordance with the knownAXI techniques have allocated a particular pathway to some other elementwithin the system and that this will impose a different time intervalindependent of all of the above until the next transaction will in factbe able to reach the slave unit concerned. At step 104, the next usagetime index for the master from which the transaction was received isupdated within the appropriate one of the registers 92, 94. At step 106the arbitrated usage signals are issued on to the target slave unit.

It will be appreciated that the usage signals as well as specifying thetime interval to the next transaction and being used to pass backacknowledgement signals indicating a time interval until the completionof a current transaction, they may also pass more standard power downcommands which will then be conveniently and scalably routed through thesystem piggy-backing on the normal data and address routinginfrastructure. Examples of such power down signals which can besupplied to the local slave power controllers, local master powercontrollers and the power controllers of the interconnect block itselfinclude commands such as local shut down, global shutdown, local sleep,global sleep, local clock stop, global clock stop, local clock speedspecifying, global clock speed specifying, low operating voltage mode,low leakage mode, wakeup and interval extend (this being a command toextend an already specified time interval until a next transaction orcompletion of a transaction).

1. A device for processing data comprising: one or more master units;one or more slave units; and an interconnect, coupled to said one ormore master units and said one or more slave units, configured to routetransactions, including data transfer transactions, along a wired pathbetween said one or more master units and said one or more slave units;wherein a transaction received by at least one of said one or more slaveunits includes one or more usage signals specifying a usage predictionindicating when a next transaction will be sent to said at least one ofsaid one or more slave units; and said at least one of said one or moreslave units has a local slave power controller responsive to said one ormore usage signals to switch said at least one of said one or more slaveunits to a first slave power state for an interval before said nexttransaction is expected to be received and to switch said at least oneof said one or more slave units to a second slave power state in time toservice said next transaction, said first slave power state having alower power consumption than said second slave power state and saidfirst slave power state having a response latency longer than saidsecond slave power state.
 2. A device as claimed in claim 1, wherein amaster unit issuing a transaction provides said one or more usagesignals within said transaction in dependence upon a current state ofsaid master unit.
 3. A device as claimed in claim 1, wherein saidinterconnect provides said one or more usage signals within saidtransaction in dependence upon a current state of said device.
 4. Adevice as claimed in claim 3, wherein said interconnect arbitratesbetween usage signals received with respective transactions from aplurality of master units to provide arbitrated usage signals passed tosaid at least one of said one or more slave units and indicative of whena next transaction will be sent to said at least one of said one or moreslave units from any of said plurality of master units.
 5. A device asclaimed in claim 1, wherein said at least one of said one or more slaveunits has a plurality of low power states with respective powerconsumptions and response latencies that can be used as said first slavepower state and said local slave power controller selects which one ofsaid plurality of low power states to use as said first slave powerstate in dependence upon said interval before said next transaction isexpected.
 6. A device as claimed in claim 5, wherein said local slavepower controller also selects which one of said plurality of low powerstates to use as said first slave power state in dependence upon acurrent state of said at least one of said one or more slave units.
 7. Adevice as claimed in claim 1, comprising a plurality of slave units eachincluding a local slave power controller responsive to said one or moreusage signals.
 8. A device as claimed in claim 1, wherein said one ormore delay predicting signals also serve to trigger one or moreintervening circuit elements on a path between said at least one of saidone or more slave units and said one of said one or more master units toenter a reduced power consumption state.
 9. A device as claimed in claim1, wherein said interconnect includes: a plurality of portions withseparately controllable power state; and a local interconnect powercontroller responsive to said one or more usage signals to controlrespective power states of said plurality of portions of saidinterconnect.
 10. A device as claimed in claim 1, wherein said one ormore usage signals comprise a plurality of usage signals and use alogarithmic encoding for at least some values of said usage prediction.11. A device as claimed in claim 1, wherein a usage predictioncorresponding to a lowest non-zero value represented by said one or moreusage signals corresponds to a lowest effective inactivity interval forone of said one or more slave units.
 12. A device as claimed in claim 1,wherein said one or more usage signals have a value indicating anindeterminate time before said next transaction and said local slavepower controller is responsive thereto to switch said at least one ofsaid one or more slave units to a low power consumption mode.
 13. Adevice as claimed in claim 1, comprising at least one usage-specifyingregister associated with a respective one of said one or more masterunits and storing a software writable value specifying usage signals tobe generated by said one of said one or more master units.
 14. A deviceas claimed in claim 1, comprising a processor responsive to a programinstruction to initiate one of said transactions, a field with saidprogram instruction specifying a value for said one or more usagesignals to be associated with said transaction.
 15. A device as claimedin claim 14, wherein said program instruction is part of an operatingsystem program and said field is varied in dependence upon a currentstate of at least a portion of said device as determined by saidoperating system program.
 16. A device as claimed in claim 1, whereinsaid one or more usage signals can also pass one or more power commands.17. A device as claimed in claim 16, wherein said one or more powercommands include one or more of: local shutdown; global shutdown; localsleep; global sleep; local clock stop; global clock stop; local clockspeed specifying; global clock speed specifying; low operating voltagemode; low leakage mode; wake up; and interval extend.
 18. A device asclaimed in claim 1, wherein said device is one of: an integratedcircuit; a multi-chip module; and a printed circuit board carrying aplurality of connected integrated circuits.
 19. A device as claimed inclaim 1, wherein said interconnect is a point-to-point interconnect. 20.A device as claimed in claim 1, wherein said interconnect is a dedicatedconnection between one master unit and one slave unit.
 21. A device asclaimed in claim 20, wherein said one master unit is a processor coreand said one slave unit is a cache memory.
 22. A device as claimed inclaim 1, wherein said usage signals are routed in a shared wired pathwith one or more other signals forming part of said transaction.
 23. Adevice as claimed in claim 1, wherein said local power controller isshared by a plurality of slave units.
 24. A method for processing datausing one or more master units, one or more slave units and aninterconnect coupled to said one or more master units and said one ormore slave units configured to route transactions, including datatransfer transactions, along a wired path between said one or moremaster units and said one or more slave units, said method comprisingthe steps of: generating a transaction received by at least one of saidone or more slave units, said transaction includes one or more usagesignals specifying a usage prediction indicating when a next transactionwill be sent to said at least one of said one or more slave units; andin response to said one or more usage signals using a local slave powercontroller of said at least one of said one or more slave units toswitch said at least one of said one or more slave units to a firstslave power state for an interval before said next transaction isexpected to be received and to switch said at least one of said one ormore slave units to a second slave power state in time to service saidnext transaction, said first slave power state having a lower powerconsumption than said second slave power state and said first slavepower state having a response latency longer than said second slavepower state.
 25. A method as claimed in claim 24, wherein said one ormore usage signals within said transaction are provided by a master unitin dependence upon a current state of said master unit.
 26. A method asclaimed in claim 24, wherein said one or more usage signals within saidtransaction are provided by said interconnect in dependence upon acurrent state of said device.
 27. A method as claimed in claim 26,comprising arbitrating with said interconnect between usage signalsreceived with respective transactions from a plurality of master unitsto provide arbitrated usage signals passed to said at least one of saidone or more slave units and indicative of when a next transaction willbe sent to said at least one of said one or more slave units from any ofsaid plurality of master units.
 28. A method as claimed in claim 24,wherein said at least one of said one or more slave units has aplurality of low power states with respective power consumptions andresponse latencies that can be used as said first slave power state andsaid local slave power controller selects which one of said plurality oflow power states to use as said first slave power state in dependenceupon said interval before said next transaction is expected.
 29. Amethod as claimed in claim 28, wherein said local slave power controlleralso selects which one of said plurality of low power states to use assaid first slave power state in dependence upon a current state of saidat least one of said one or more slave units.
 30. A method as claimed inclaim 24, wherein a plurality of slave units each including a localslave power controller are responsive to said one or more usage signals.31. A method as claimed in claim 24, wherein said one or more delaypredicting signals also serve to trigger one or more intervening circuitelements on a path between said at least one of said one or more slaveunits and said one of said one or more master units to enter a reducedpower consumption state.
 32. A method as claimed in claim 24, whereinsaid interconnect includes a plurality of portions with separatelycontrollable power state, said method further comprising in response tosaid one or more usage signals using a local interconnect powercontroller of said interconnect to control respective power states ofsaid plurality of portions of said interconnect.
 33. A method as claimedin claim 24, wherein said one or more usage signals comprise a pluralityof usage signals and use a logarithmic encoding for at least some valuesof said usage prediction.
 34. A method as claimed in claim 24, wherein ausage prediction corresponding to a lowest non-zero value represented bysaid one or more usage signals corresponds to a lowest effectiveinactivity interval for one of said one or more slave units.
 35. Amethod as claimed in claim 24, wherein said one or more usage signalshave a value indicating an indeterminate time before said nexttransaction, said method further comprising in response to said valueindicating an indeterminate time using said local slave power controllerto switch said at least one of said one or more slave units to a lowpower consumption mode.
 36. A method as claimed in claim 24, comprisingstoring under software control into at least one usage-specifyingregister associated with a respective one of said one or more masterunits a value specifying usage signals to be generated by said one ofsaid one or more master units.
 37. A method as claimed in claim 24,comprising in response to a program instruction executed by a processorinitiating one of said transactions, a field with said programinstruction specifying a value for said one or more usage signals to beassociated with said transaction.
 38. A method as claimed in claim 37,wherein said program instruction is part of an operating system programand said field is varied in dependence upon a current state of at leasta portion of said device as determined by said operating system program.39. A method as claimed in claim 24, wherein said one or more usagesignals can also pass one or more power commands.
 40. A method asclaimed in claim 39, wherein said one or more power commands include oneor more of: local shutdown; global shutdown; local sleep; global sleep;local clock stop; global clock stop; local clock speed specifying;global clock speed specifying; low operating voltage mode; low leakagemode; wake up; and interval extend.
 41. A method as claimed in claim 24,wherein said method is performed within one of: an integrated circuit; amulti-chip module; and a printed circuit board carrying a plurality ofconnected integrated circuits.
 42. A method as claimed in claim 24,wherein said interconnect is a point-to-point interconnect.
 43. A methodas claimed in claim 24, wherein said interconnect is a dedicatedconnection between one master unit and one slave unit.
 44. A method asclaimed in claim 43, wherein said one master unit is a processor coreand said one slave unit is a cache memory.
 45. A method as claimed inclaim 24, wherein said usage signals are routed in a shared wired pathwith one or more other signals forming part of said transaction.
 46. Amethod as claimed in claim 24, wherein said local power controller isshared by a plurality of slave units.
 47. A device for processing datacomprising: one or more master unit means for generating transactions;one or more slave unit means for receiving said transactions; and aninterconnect means, coupled to said one or more master units and saidone or more slave units, for routing one or more of said transactions,including data transfer transactions, along a wired path between saidone or more master unit means and said one or more slave unit means;wherein a transaction received by at least one of said one or more slaveunit means includes one or more usage signals specifying a usageprediction indicating when a next transaction will be sent to said atleast one of said one or more slave unit means; and said at least one ofsaid one or more slave unit means has a local slave power controllermeans responsive to said one or more usage signals to switch said atleast one of said one or more slave unit means to a first slave powerstate for an interval before said next transaction is expected to bereceived and to switch said at least one of said one or more slave unitmeans to a second slave power state in time to service said nexttransaction, said first slave power state having a lower powerconsumption than said second slave power state and said first slavepower state having a response latency longer than said second slavepower state.
 48. A slave unit for use within a device having one or moremaster units, one or more slave units and an interconnect coupled tosaid one or more master units and said one or more slave units so as toroute transactions, including data transfer transactions, along a wiredpath between said one or more master units and said one or more slaveunits, a transaction to received by at least one of said one or moreslave units including one or more usage signals specifying a usageprediction indicating when a next transaction will be sent to said atleast one of said one or more slave units, said slave unit comprising: alocal slave power controller responsive to said one or more usagesignals to switch said at least one of said one or more slave units to afirst slave power state for an interval before said next transaction isexpected to be received and to switch said at least one of said one ormore slave units to a second slave power state in time to service saidnext transaction, said first slave power state having a lower powerconsumption than said second slave power state and said first slavepower state having a response latency longer than said second slavepower state.
 49. A device for processing data comprising: one or moremaster units; one or more slave units; and an interconnect coupled tosaid one or more master units and said one or more slave units so as toroute transactions, including data transfer transactions, along a wiredpath between said one or more master units and said one or more slaveunits; wherein a transaction received by at least one of said one ormore slave units includes one or more usage signals specifying a usageprediction indicative of when a next transaction will be sent to said atleast one of said one or more slave units; and said at least one of saidone or more slave units has a local slave power controller responsive tosaid one or more usage signals to switch said at least one of said oneor more slave units to a first slave power state for an interval beforesaid next transaction is expected to be received and to switch said atleast one of said one or more slave units to a second slave power statein time to service said next transaction, said first slave power statehaving a lower power consumption than said second slave power state andsaid first slave power state having a response latency longer than saidsecond slave power state, wherein at least one of said one or more slaveunits upon receipt of a transaction from one of said one or more masterunits issues an acknowledgement to said one of said one or more masterunits, said acknowledgement including one or more delay predictingsignals indicative of when said at least one of said one or more slaveunits will complete said transaction to said one of said one or moremaster units, and said one of said one or more master units includes alocal master power controller responsive to said one or more delayedpredicting signals to switch said one of said one or more master unitsto a first master power state for an interval before completion of saidtransaction is expected and to switch said one of said one or moremaster units to a second master power state in time for completion ofsaid transaction, said first master power state having a lower powerconsumption than said second master power state and said first masterpower state having a response latency longer than said second masterpower state.
 50. A method for processing data using one or more masterunits, one or more slave units and an interconnect coupled to said oneor more master units and said one or more slave units so as to routetransactions, including data transfer transactions, along a wired pathbetween said one or more master units and said one or more slave units,said method comprising the steps of: generating a transaction receivedby at least one of said one or more slave units, said transactionincludes one or more usage signals specifying a usage predictionindicative of when a next transaction will be sent to said at least oneof said one or more slave units; and in response to said one or moreusage signals using a local slave power controller of said at least oneof said one or more slave units to switch said at least one of said oneor more slave units to a first slave power state for an interval beforesaid next transaction is expected to be received and to switch said atleast one of said one or more slave units to a second slave power statein time to service said next transaction, said first slave power statehaving a lower power consumption than said second slave power state andsaid first slave power state having a response latency longer than saidsecond slave power state, wherein at least one of said one or more slaveunits upon receipt of a transaction from one of said one or more masterunits issues an acknowledgement to said one of said one or more masterunits, said acknowledgement including one or more delay predictingsignals indicative of when said at least one of said one or more slaveunits will complete said transaction to said one of said one or moremaster units, and in responsive to said one or more delayed predictingsignals using a local master power controller of said one of said one ormore master units to switch said one of said one or more master units toa first master power state for an interval before completion of saidtransaction is expected and to switch said one of said one or moremaster units to a second master power state in time for completion ofsaid transaction, said first master power state having a lower powerconsumption than said second master power state and said first masterpower state having a response latency longer than said second masterpower state.